Low Power 8x8 Bit CMOS Multiplier Using 65nm Technology
نویسنده
چکیده
This paper presents low power 8x8 bit multipliers which are implemented with Tanner Tool v13.0 at 500MHz frequency with 65nm technology which is having a supply voltage 1.0v. There are different CMOS multiplier circuits are analyzed names as Braun multiplier, Wallace tree multiplier, Row bypass Braun multiplier, Column bypass Braun multiplier, Row and Column bypass Braun multiplier and these multiplier are realized using bridge style full adder with semi domino logic . All these multipliers are compared in terms of delay, power dissipation and power delay product. Simulation results show that the Braun multiplier with using bridge style adder with semi domino logic has minimum power delay product and is faster as compared to other CMOS multipliers.
منابع مشابه
Performance Analysis of Different 8x8 Bit CMOS Multiplier using 65nm Technology
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